In an image sensor adapted to a global shutter control, each pixel comprises a photosensitive area, a read area, and a storage area. The photogenerated charges accumulated during an integration phase in the photosensitive areas of all the sensor pixels are simultaneously transferred into the corresponding storage areas and a full image is then stored in all the sensor storage areas. The stored image may then be read, line by line, during the next integration phase. Pixel structures compatible with a global shutter control where insulated vertical electrodes enable to transfer charges from the photosensitive area to the storage area, and from the storage area to the read area, are taught by U.S. Pat. No. 9,236,407 (incorporated by reference).
FIGS. 1A to 1G are copies of FIGS. 3A to 3G of patent U.S. Pat. No. 9,236,407 illustrating an example of a pixel 200 formed inside and on top of a silicon semiconductor substrate 201. FIG. 1A shows this pixel in top view. FIGS. 1B to 1G are cross-section views respectively along planes B-B, C-C, D-D, E-E, F-F, and G-G of FIG. 1A.
Pixel 200 comprises a photosensitive area, an intermediate charge storage area, and a read area connected to a read and processing circuit.
Substrate 201 is lightly P-type doped (P−). The photosensitive area of pixel 200 comprises an N-type doped well 205, having a doping level N1, forming with substrate 201 the junction of a photodiode, or photosite, PD′. The storage area of the pixel comprises, juxtaposed to well 205, an N-type doped well 207, having a doping level N2 greater than N1, forming with substrate 201 the junction of a diode SD′. Wells 205 and 207 substantially have the same depth and have a common side. A thin heavily-doped P-type layer 213 (P+) is formed at the surface of wells 205 and 207 so that photosite PD′ and diode SD′ are of pinned type. The read area of pixel 200 comprises, adjacent to well 207, on the side of well 207 opposite to well 205, a region 211 formed at the surface of substrate 201 and more heavily N-type doped (N+) than wells 205 and 207.
An insulated vertical electrode 203 extends in the substrate down to a depth greater than that of wells 205 and 207, between wells 205 and 207, at the level of their common side. Electrode 203 insulates well 205 from well 207, except in a charge transfer area 204 where electrode 203 comprises an opening extending along its entire height and connecting well 205 to well 207. Electrode 203 has, in top view, a U shape delimiting most of three sides of well 207, the horizontal line of the U being located at the level of the side common to well 205 and 207.
Another insulated vertical electrode 209 extends in the substrate between well 207 and reading region 211, at the level of their common side, down to a depth greater than that of well 207. Electrode 209 insulates well 207 from region 211, except at the level of a charge transfer area 206 where electrode 209 comprises an opening extending along its entire height and connecting well 207 to region 211. Electrode 209 has the shape of a vertical plane delimiting most of the side of well 207 adjacent to region 211 (that is, the side of well 207 opposite to transfer area 204).
Another insulated vertical electrode 202 extending down to a depth at least equal to that of well 205 laterally delimits most of the three sides of well 205 which are not delimited by electrode 203.
Electrodes 202, 203, and 209 and region 211 are connected by metallizations (not shown), respectively to a node Vp, to nodes TG1 and TG2, and to a node SN connected or coupled to a read circuit. Read circuit (FIG. 1A) comprises a transistor 213 connecting node SN to a high power supply rail VDD of the sensor, a transistor 215 assembled as a source follower, having its gate connected to node SN, and having its drain connected to rail VDD, and a transistor 217 connecting the source of transistor 215 to a reading line 219 of an array network comprising pixel 200. The gate of transistor 213 is connected to a node RST of application of a signal for resetting region 211, and the gate of transistor 217 is connected to a node RS of application of a pixel selection signal 200. Transistors 213, 215, and 217 are formed in a P-type doped well 220 (PW), laterally delimited by an insulating region 221.
In charge accumulation or integration phase, nodes Vp and TG1 are at a same low voltage in the order of −1 V. Such a biasing of electrodes 202 and 203 causes an accumulation of holes along the walls of the vertical trenches delimiting the photosensitive area. Holes also accumulate in transfer area 204, thus blocking electron exchanges between wells 205 and 207. Since substrate 201 is biased to the ground voltage, a potential well forms in well 205, which, in the absence of illumination, depends on the doping levels and on the bias voltages of the electrodes and of the substrate. When photodiode PD′ is illuminated, electron/hole pairs are photogenerated in the photodiode, and the photogenerated electrons are attracted towards well 205 and trapped therein.
In a phase of transfer of the photogenerated electrons accumulated in well 205 to the storage area, node TG1 is set to a high voltage such that the depletion voltage of transfer area 204 has a value greater than the maximum potential of the potential well in photodiode PD′ to transfer the electrons contained in well 205 into well 207, via transfer area 204. Node VP is maintained at the low voltage. Node TG2 is also at a low voltage, which causes the accumulation of holes in transfer area 206, thus blocking electron exchanges between well 207 and region 211. Once the transfer has been performed, node TG1 is set back to the low voltage, to maintain the transferred electrons confined in well 207. At this stage, a new integration phase may start.
In read phase, the charges contained in well 207 are transferred to read area 211, via transfer area 206. To achieve this, node TG2 is set to a high voltage such that the depletion voltage in transfer area 206 has a value greater than the maximum potential of the potential well in diode SD′. Nodes Vp and TG1 are maintained at the low voltage. Once the transfer has been performed, node TG2 is set back to the low voltage.
A pixel of type in FIGS. 1A to 1G suffers from various disadvantages, especially as concerns the charge transfer from the photosensitive area to the storage area.
It would thus be desirable to have a pixel structure compatible with a global shutter control which overcomes at least some of the disadvantages of existing structures.